Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One such silicon-based semiconductor device is a metal-oxide-semiconductor (MOS) transistor.
The principal elements of a typical MOS semiconductor device are illustrated in FIG. 1. The device generally includes a semiconductor substrate 101 on which a gate electrode 103 is disposed. The gate electrode 103 acts as a conductor. An input signal is typically applied to the gate electrode 103 via a gate terminal (not shown). Heavily-doped source/drain regions 105 are formed in the semiconductor substrate 101 and are connected to source/drain terminals (not shown). As illustrated in FIG. 1, the typical MOS transistor is symmetrical, which means that the source and drain are interchangeable. Whether a region acts as a source or drain depends on the respective applied voltages and the type of device being made (e.g., PMOS, NMOS, etc.). Thus, as used herein, the term source/drain region refers generally to a region used for the formation of a source or drain.
After the source/drain regions have been formed, a relatively thick oxide layer (not shown), often referred to as a contact formation layer, is disposed over the substrate 101. Contact openings are generally cut into the thick oxide layer to expose the source/drain regions 105 and the surface of the gate electrode 103. The contact openings are then filled with a metal, such as tungsten or aluminum, which is used as a terminal to connect active regions on the chip.
Contact openings are typically formed using photolithography. Generally, a photoresist material is deposited over the contact formation layer, patterned, and removed to expose portions of the contact formation layer. The exposed portions of the contact formation layer are then etched to the surface of the active region (e.g., a gate electrode or source/drain region) to form the contact opening. A more detailed description of contact formation and the fabrication thereof may be found in S. Wolf, Silicon Processing for the VLSI Era, Vol. 2: Processing Integration, pp. 102-111.
Semiconductor devices, like the one described above, are used in large numbers to construct most modern electronic devices. As a larger number of such devices are integrated into a single silicon wafer, improved performance and capabilities of electronic devices can be achieved. In order to increase the number of semiconductor devices which may be formed on a given surface area of a substrate, the semiconductor devices must be scaled down (i.e., made smaller). This is accomplished by reducing the lateral and vertical dimensions of the device structure.
New semiconductor fabrication processes and devices are continually needed to advance the trend of reduced semiconductor device size and increased performance. For example, the size of contact openings is one important dimension which must be scaled down as the device structure is made smaller. The minimum size of conventionally-formed contact openings is dependent upon the minimum-resolution of the patterning and etching technology used to open the contact openings. The resolution of conventional patterning and etching technology thus limits further scaling of device dimensions.